1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for use in a LCD device having thin film transistors (TFTs) and to a method of manufacturing the same.
2. Description of Related Art
In general, a liquid crystal display (LCD) device displays an image using a plurality of pixels. An LCD device that uses thin film transistors (TFTs) as switching elements is typically called a thin film transistor liquid crystal display (TFT-LCD) device.
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules. Because of their peculiar characteristics liquid crystal molecules have a definite orientational order in arrangement. The arrangement direction of liquid crystal molecules can be controlled by an applied electric field. In other words, when electric fields are applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since incident light is refracted according to the arrangement of the liquid crystal molecules, due to the optical anisotropy of liquid crystal molecules, image data can be displayed.
An active matrix LCD (AM-LCD) has its thin film transistors (TFTs) and pixel electrodes arranged in a matrix. Such LCDs can have high resolution and superior imaging of moving images.
FIG. 1 is a cross-sectional view illustrating a conventional liquid crystal display (LCD) panel. As shown in FIG. 1, the LCD panel 20 has lower and upper substrates 2 and 4 with a liquid crystal layer 10 interposed therebetween. The lower substrate 2, which is referred to as an array substrate, has a TFT “S” as a switching element that changes the orientation of the liquid crystal molecules. A pixel electrode 14 applies a voltage to the liquid crystal layer 10 according to the state of the TFT “S”. The upper substrate 4 has a color filter 8 for implementing a color and a common electrode 12 on the color filter 8. The common electrode 12 serves as an electrode for applying a voltage to the liquid crystal layer 10. The pixel electrode 14 is arranged over a pixel portion “P”, of a display area. Further, to prevent leakage of the liquid crystal layer 10, the two substrates 2 and 4 are sealed using a sealant 6.
FIG. 2 is a partial plan view illustrating an array substrate of a conventional LCD device. A gate line 22 is arranged in a transverse direction and a data line 24 is arranged in perpendicular to the gate line 22. A pixel region having a pixel electrode 14 is defined by the gate line 22 and the data line 24.
In an AM-LCD, the switching element (TFT “S”) that selectively applies the voltage to the liquid crystal layer 10 (see FIG. 1) is formed near the crossing of the gate line 22 and the data line 24. The TFT “S” has a gate electrode 26 that is extended from the gate line 22, a source electrode 28 that is extended from the data line 24, and a drain electrode 30 that is electrically connected to the pixel electrode 14 via a contact hole 31. The gate line 22 and the pixel electrode 14 form a storage capacitor “Cst” which stores electric charges. The passivation layer 40 is arranged to protect the data line 24 and the TFT “S”.
When the gate electrode 26 of the TFT “S” receives gate signals via the gate line 22, the TFT “S” turns ON. The data signals on the data line 24 are then applied to the pixel electrode 14. The applied electric field from the pixel electrode 14 then changes the arrangement direction of the liquid crystal molecules, causing the liquid crystal molecules to refract the light generated by a back light device. When the gate line 22 turns the TFT “S” to the OFF-state, data signals are not transmitted to the pixel electrode 14. In this case, the arrangement of the liquid crystal is not changed, and thus the direction of the light from back light device is not changed.
When fabricating a liquid crystal panel, a number of complicated process steps are required. In particular, the TFT array substrate requires numerous mask processes. Each mask process requires a photolithography process. Thus, to reduce cost and manufacturing time, the number of mask processes should be minimized.
In general, a manufacturing process depends on the materials used and on the design goals. For example, the resistivity of the material used for the gate lines and the data lines impacts the picture quality of large LCD panels (over 12 inches) and of LCD panels having high resolution. With such LCD panels, a material such as Aluminum (Al) or Al-alloy is often used for the gate lines.
FIGS. 3A to 3D are cross-sectional views taken along line III—III and illustrate the process steps of fabricating a conventional TFT array substrate for an active matrix LCD device.
An inverted staggered type TFT is generally used due to its simple structure and superior efficiency. The inverted staggered type TFT can be classified as either a back channel etched type (EB) and an etch stopper type (ES), depending on the fabrication method that is used. The fabrication method of the back channel etched type TFT will now be explained.
A first metal layer is deposited on a substrate 1 by a sputtering process. The substrate previously underwent a cleaning process to enhance adhesion between the substrate 1 and the first metal layer. That cleaning process removes organic materials and alien substances from the substrate.
FIG. 3A shows a step of forming a gate electrode 26 by patterning the first metal layer. The gate electrode 26 is usually Aluminum, which reduces the RC delay owing to a low resistance. However, pure Aluminum is delicate to the acid, and it may result in line defects caused by formation of hillocks during a subsequent high temperature process. Thus, an Aluminum alloy or another material is beneficially used.
Referring to FIG. 3B, an insulator layer 50 is formed over the surface of the substrate 1 and over the gate electrode 26. Then, a pure amorphous silicon (a-Si:H) layer 52 as an active layer and a doped amorphous silicon (n+ a-Si:H) layer 54 as an ohmic contact layer are formed in sequence on the insulator layer 50. The ohmic contact layer 54 reduces the contact resistance between the active layer 52 and electrodes that will be formed later. After that, a data line 24 and source and drain electrodes 28 and 30 are formed by depositing and patterning a second metal layer. A portion of the doped amorphous silicon layer 54 on the pure amorphous silicon layer 52 is etched using the data line 24 and source and drain electrodes 28 and 30 as masks. At this time, a channel region “CH” is formed by removing the portion of the doped amorphous silicon layer 54 using the source and drain electrodes 28 and 30 as masks. If the doped amorphous silicon layer 54 between the source and drain electrodes 28 and 30 is not removed, serious problems that deteriorates electrical characteristics of the TFT “S” (see FIG. 2) can result. Thus, these cause low efficiencies of the TFT “S” (see FIG. 2). Etching the portion of the doped amorphous silicon layer 54 over the gate electrode 26 requires special attention. While etching the doped amorphous silicon layer 54, the pure amorphous silicon layer 52 is typically over-etched by about 50˜100 due to the fact that the pure amorphous silicon layer 52 and the doped amorphous silicon layer 54 have no etch selectivity. In this step, moreover, etching uniformity is very important because it affects the characteristics and properties of the TFT. And then a passivation layer 40 is formed over the pure amorphous silicon layer 52, over the data line 24 and over the source and drain electrodes 28 and 30.
Referring to FIG. 3C, the passivation layer 40 is etched to form a drain contact hole 31 that is used to connect the drain electrode 30 to a pixel electrode that is formed later. At this time, as shown in FIG. 3C, a portion of the passivation layer 40, except the portion covering the data line 24 and the source and drain electrodes 28 and 30, is etched. Moreover, the active layer 52 (the pure amorphous silicon layer) and the insulator layer 50, except the portion below the second metallic layer, are etched at the same time.
FIG. 3D also shows a step of forming a pixel electrode 14 by depositing and then patterning a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). Therefore, as shown in FIG. 3D, the pixel electrode 14 contacts the drain electrode 30 via the drain contact hole 31, while the pixel electrode 14 depicted at the left side of FIG. 3D is spaced apart from the data line 24.
As described above, since the conventional array substrate for use in the LCD device is fabricated using a four-mask process, manufacturing yields increase and misalignment is reduced. However, as shown in FIG. 4 that is enlarged view illustrating potion “A” of FIG. 2, an abnormal pixel electrode 15 can be formed when forming the pixel electrode 14. The abnormal pixel electrode 15 causes the LCD device to have point defects by connecting the pixel electrode 14 to the pure amorphous silicon layer 52. The detailed explanation will be explained referring to FIG. 5.
FIG. 5 is a cross-sectional view taken along line—of FIG. 4 and illustrates the point defects caused by the abnormal pixel electrode 15. As shown, the pure amorphous silicon layer 52 is exposed by the etching process that simultaneously etches the passivation layer 40, the pure amorphous silicon layer 52 and the insulator layer 50, as described in FIG. 3C. If the abnormal pixel electrode 15 is formed when forming the pixel electrode 14, the pure amorphous silicon 52 and the pixel electrode 14 is short-circuited by the abnormal pixel electrode 15 and thus the signal voltages applied to the pixel electrode 14 is leaked. Therefore, this results in the deterioration of picture quality and of definition.
In order to prevent the short-circuit between the pixel electrode 14 and the amorphous silicon layer 54 (i.e., the active layer), the pixel electrode 14 is spaced apart from the active layer 54 by the distance of length “L” in the conventional LCD device. Thus, the aperture ratio is lowered as much as the distance of length “L”. Moreover, since the data line 24 is formed in very close to the pure amorphous silicon layer 52 (i.e., active layer), the electric field appears in the pure amorphous silicon layer 52(i.e., active layer) when the data signals are applied to the data line 24. The electric field appearing in the active layer 52 causes cross-talk with the adjacent pixel electrode 14.